High-voltage devices are highly desirable for numerous applications, including LCD (liquid crystal display) driver ICs, power management devices, power supplies, nonvolatile memories, communication circuits, and control circuits. Particularly, the LCD driver IC requires low-voltage/middle-voltage operation for driving an associated logic circuit together with high-voltage operation for driving the LCD during operation. Since devices with different breakdown voltages are required on a single chip, making the high-voltage device process compatible with current low-voltage device processes and middle-voltage device processes has become an important issue.
In general, most high-voltage metal-oxide-semiconductor (MOS) transistors thicken an isolating layer between the gate and the source/drain regions as a means of lowering the horizontal electric field within the channel. Alternatively, drift regions below the isolation layer and the graded regions beneath source/drain regions are lightly doped to provide the necessary voltage gradient. The two above measures are capable of increasing junction breakdown voltage in the source/drain regions so that the MOS transistor is able to operate normally despite the application of a high voltage, e.g., greater than 5V. One type of high-voltage transistors is DDDMOS (double diffused drain MOS) transistors, which are grouped into VDMOS (vertical DMOS) transistors and LDMOS (lateral DMOS) transistors according to the direction of the current path. U.S. Pat. No. 6,468,870 to Kao, et al. incorporated herein by reference describes a method of fabricating an LDMOS transistor with an inter-level dielectric layer.
Conventionally, the source/drain regions are electrically connected to an upper conductive layer that fills a contact hole fabricated in an interlayer dielectric (WLD) layer. It is frequently desired to form an etch stop layer over circuit constructions so that subsequent etching conditions for the contact hole do not damage the circuit constructions. U.S. Pat. No. 6,630,398 to Tsai, et al. incorporated herein by reference describes a borderless contact with a silicon oxynitride etch stop layer. U.S. Pat. No. 6,235,653 to Chien, et al. and U.S. Pat. No. 6,316,348 to Fu, et al. incorporated herein by reference describe a silicon-rich oxynitride film having a silicon molar percentage between about 58% and 62% for an etch stop layer. Such a silicon-rich SiON film is insufficient for buffer isolation in high-voltage device applications because the silicon-rich SiON film generates an extra leakage path through which leakage current flows. The extra leakage path causes a large leakage current from the gate to the source and thereby lowers the gate oxide breakdown voltage. Chip reliability tests reveal that a silicon-rich SiON etch stop layer integrated into high-voltage MOS transistors fails in GOI (gate oxide integrity) tests and introduces a time dependence of drain current.